The demand for faster, more powerful integrated circuit (IC) devices has introduced new challenges for IC fabrication technology, including the need to etch high-aspect-ratio features, such as trenches or vias, on a substrate or wafer. For example, deep-trench storage node capacitors used in some dynamic random access memory structures require high-aspect ratio trenches in silicon. Deep silicon trench etching is typically carried out in a reactive ion etching (RIE) process with a SiO2 hard mask. The challenges in trench etching include achieving a high etching rate even for ultrahigh-aspect-ratio features and controlling trench sidewall taper angles to very tight limits.
Typically, a deep silicon trench etch process is performed in a bromine-containing plasma, which is a plasma of a combination of gases including a bromine-based compound, such as HBr, as an etchant gas for removing exposed silicon from the wafer. The combination of gases also includes a passivant gas such as O2 for protecting the trench sidewalls from the etchant gas. The O2, together with Si-containing etching products, forms a passivation layer deposited on the sidewalls of the trenches. To prevent this layer from becoming too thick, a deposit removal gas such as NF3 is typically included in the combination of gases used for Si trench etching. The amount of deposits on the trench sidewalls and the taper angles can usually be controlled by adjusting the wafer surface temperature and the O2 partial pressure in the HBr/NF3/O2 plasma.
However, as feature sizes continue to shrink, the deposits on the trench sidewalls may close up or choke the trench openings and prevent the trenches from being etched deeper. For example, FIG. 1 depicts a trench 10 with tapered trench sidewalls 15 being etched by a plasma 20 in a silicon wafer 30. An oxide hard mask 40 on top of silicon wafer 30 protects the silicon from being etched except in the area of trench 10. As the etching proceeds, a passivation layer 50 builds up on the sidewalls of the trench and may choke the trench opening as shown in FIG. 1. Choking is known as one of the factors limiting the aspect ratio of trenches that can be etched with an RIE process. Increasing the NF3 partial pressure may help reduce choking in some situations, but having a large amount of NF3 in the RIE process may result in excessive erosion of the SiO2 mask. Therefore, it is desirable to have an etching process that eliminates the problem of choking while maintaining precise control of the trench sidewall taper angles and other critical features associated with deep silicon trenches having very small critical dimensions.
Moreover, as the layer of deposits forms on the trench sidewalls, it also forms on other surfaces inside an etching chamber. Typically, a chamber for deep silicon trench etching needs to be cleaned after a certain number of wafers are etched. The cleaning is conventionally done using a dry clean process such as, for example, by running a NF3 plasma for 1.5 minutes for every 10 minutes of etching done in the chamber. In order to protect the surface of a wafer holder in the chamber during the dry clean process, a test wafer is usually placed on the wafer holder. The dry clean process itself and the transferring of wafers in and out of the chamber are time consuming, and thus slow down the throughput of wafer production. Also, the test wafer can only be used for a certain number of dry clean processes and is costly to replace. Therefore, it is desirable to maintain a clean chamber during an etching process or to clean the chamber quickly afterwards without the use of a test wafer.
Furthermore, using a bromine-containing plasma to etch deep silicon trenches typically results in a large amount of bromine condensation on the SiO2 mask. When the etching is completed, the wafer is typically removed from an etching chamber to a transfer chamber through a load lock. The bromine condensation on the SiO2 mask tends to evaporate from the SiO2 mask during this process and re-deposit on other surfaces on the load lock and in the transfer chamber, causing corrosion in the transfer chamber and on the load lock after transfer of a number of processed wafers.